Sequential Circuit Design

By Notes Vandar

5.1. Flip-flops: RS, JK, D, and T, Latches

Flip-flops and latches are the fundamental building blocks of sequential logic circuits. They are bistable devices, meaning they have two stable states, 0 and 1, and can store 1 bit of data. The difference between flip-flops and latches lies in their triggering mechanisms: flip-flops are edge-triggered, while latches are level-triggered.

1. Latches

A latch is a level-triggered device, meaning its output changes as long as the input condition is met (for example, when the enable signal is active).

SR (Set-Reset) Latch

The SR latch is the most basic type of latch, having two inputs: Set (S) and Reset (R).

  • S (Set): Makes the output Q = 1.
  • R (Reset): Makes the output Q = 0.
  • Q’ (Q complement): The inverted output.
S R Q Q’
0 0 Q Q’
0 1 0 1
1 0 1 0
1 1 Undefined

SR Latch Characteristics:

  • When S = 1 and R = 0, the latch is set.
  • When S = 0 and R = 1, the latch is reset.
  • When both S = 0 and R = 0, the latch retains its previous state (Q = previous Q).
  • S = 1 and R = 1 is an invalid state as both outputs Q and Q’ become undefined.

2. Flip-Flops

A flip-flop is an edge-triggered memory element, meaning it changes state only on the edge (rising or falling) of a clock signal. Flip-flops have the same general types as latches but with clocked inputs.

SR (Set-Reset) Flip-Flop

The SR flip-flop is an edge-triggered version of the SR latch. It functions similarly, but it only responds to the clock signal’s edge (rising or falling, depending on design).

Clock S R Q Q’
0 x x Q Q’
↑ 0 0 Q Q’
↑ 0 1 0 1
↑ 1 0 1 0
↑ 1 1 Undefined

D (Data or Delay) Flip-Flop

The D flip-flop is one of the most commonly used types of flip-flops. It eliminates the invalid state problem of the SR flip-flop by having only one input (D for Data). It ensures that the output follows the input at the clock’s rising (or falling) edge.

Clock D Q Q’
0 x Q Q’
↑ 0 0 1
↑ 1 1 0
  • D = 1: Output is set.
  • D = 0: Output is reset.

Characteristics:

  • The D flip-flop transfers the value of input D to output Q on the clock’s active edge.
  • It acts as a single-bit data storage element.

JK Flip-Flop

The JK flip-flop is a refinement of the SR flip-flop, with the invalid state removed. The J and K inputs are similar to S and R in an SR flip-flop, but with added functionality. When both J = 1 and K = 1, the output toggles.

Clock J K Q Q’
0 x x Q Q’
↑ 0 0 Q Q’
↑ 0 1 0 1
↑ 1 0 1 0
↑ 1 1 Q’ Q

Characteristics:

  • J = 1, K = 0: Set Q to 1.
  • J = 0, K = 1: Reset Q to 0.
  • J = K = 0: No change (holds previous state).
  • J = K = 1: Toggles Q (flips the state).

T (Toggle) Flip-Flop

The T flip-flop is a simplified version of the JK flip-flop where both J and K inputs are tied together to form a single toggle input (T). The T flip-flop toggles the output on every clock pulse when T = 1.

Clock T Q Q’
0 x Q Q’
↑ 0 Q Q’
↑ 1 Q’ Q

Characteristics:

  • T = 1: Toggles the output on the clock edge.
  • T = 0: No change (output remains the same).

The T flip-flop is commonly used in counters and other sequential circuits.

Summary of Flip-Flops and Latches:

Type Triggering Inputs Functionality
SR Latch Level S, R Sets or resets output based on S and R
SR Flip-Flop Edge S, R, Clock Set or reset on clock edge
D Flip-Flop Edge D, Clock Transfers D to Q on clock edge
JK Flip-Flop Edge J, K, Clock Set, reset, or toggle on clock edge
T Flip-Flop Edge T, Clock Toggles output on clock edge

These flip-flops and latches are essential components in the design of registers, counters, memory devices, and many other sequential logic circuits.

5.2 Triggering of flip-flops

Triggering refers to the mechanism by which a flip-flop changes its state. Flip-flops are edge-sensitive devices, meaning their state changes occur only in response to specific changes (edges) of a clock signal. The two types of triggering in flip-flops are edge triggering and level triggering. Most flip-flops used in digital systems are edge-triggered, which provides better control and synchronization in sequential circuits.

Types of Triggering in Flip-Flops

  1. Edge Triggering
  2. Level Triggering

1. Edge Triggering

In edge-triggered flip-flops, the state of the flip-flop is only affected by changes in the clock signal, specifically when the clock transitions from one state to another. There are two types of edge triggering:

  • Positive Edge Triggering (Rising Edge Triggering)
  • Negative Edge Triggering (Falling Edge Triggering)

Positive Edge Triggering (Rising Edge Triggering)

In positive edge triggering, the flip-flop is triggered when the clock signal transitions from low (0) to high (1). This is known as the rising edge or positive edge of the clock. The flip-flop only updates its state when it detects this rising edge, ensuring that the output is stable between clock transitions.

Symbol: A small triangle at the clock input in the flip-flop symbol indicates positive edge triggering.

Negative Edge Triggering (Falling Edge Triggering)

In negative edge triggering, the flip-flop is triggered when the clock signal transitions from high (1) to low (0). This is known as the falling edge or negative edge of the clock. The flip-flop changes its state only on this falling edge, which is used in cases where synchronization on the falling edge is preferred.

Symbol: A small triangle at the clock input with a bubble (inversion) indicates negative edge triggering.

2. Level Triggering

In level-triggered flip-flops, the state of the flip-flop is affected as long as the clock signal is at a specific level—either high (1) or low (0). This means the output can continuously change as long as the clock is at the active level, which may cause instability if the inputs fluctuate during the active period.

There are two types of level triggering:

  • High-Level Triggering (Active-High Triggering)
  • Low-Level Triggering (Active-Low Triggering)

High-Level Triggering (Active-High Triggering)

In high-level triggering, the flip-flop is enabled and can change its state while the clock signal is at the high level (1). The flip-flop continues to respond to input changes as long as the clock is high.

Low-Level Triggering (Active-Low Triggering)

In low-level triggering, the flip-flop is enabled and can change its state while the clock signal is at the low level (0). As long as the clock remains low, the flip-flop can respond to inputs.

Edge Triggered vs. Level Triggered

Aspect Edge Triggering Level Triggering
State Change Only on clock edges (rising or falling) While the clock is at a specific level (high or low)
Stability More stable, as input changes outside the clock edge do not affect the output Less stable, as the output can change continuously during the active clock level
Symbol Triangle for positive edge, triangle + bubble for negative edge No specific symbol for level triggering
Use Common in modern digital circuits (synchronous systems) Rarely used in modern flip-flops due to the risk of glitches

Triggering in Different Flip-Flops

  1. SR Flip-Flop: Can be either level-triggered or edge-triggered. Edge-triggered versions are more common to prevent instability during clock transitions.
  2. D Flip-Flop: Typically edge-triggered (either positive or negative). It ensures that the data input (D) is captured only at the moment of the clock edge, making it highly useful in memory elements and registers.
  3. JK Flip-Flop: Usually edge-triggered to avoid the undefined state that occurs in SR flip-flops. Edge triggering allows toggling behavior to occur only at specific clock transitions.
  4. T Flip-Flop: Generally edge-triggered to ensure that toggling occurs only on the rising or falling edge of the clock signal.

Clock Skew and Its Impact on Triggering

In sequential circuits using edge-triggered flip-flops, the timing of clock edges is crucial. Any delay or variation in the clock signal’s arrival at different flip-flops is known as clock skew. Clock skew can lead to timing issues, where some flip-flops are triggered at different times than intended. Proper design and clock distribution techniques are necessary to minimize clock skew and maintain synchronization.

5.3 Master slave flip flop

The Master-Slave flip-flop is a type of edge-triggered flip-flop that helps eliminate race conditions, which can occur when outputs change state unpredictably due to input changes during the clock cycle. It achieves this by splitting the flip-flop into two stages: the master and the slave. The master stage responds to the clock during one phase, and the slave stage responds during the opposite phase. This structure ensures that the output changes only once per clock cycle.

Structure and Working of Master-Slave Flip-Flop

The Master-Slave flip-flop typically consists of two identical flip-flops (usually SR, JK, or D flip-flops) connected in series:

  • The master flip-flop is active when the clock is in one phase (typically the rising edge or high level of the clock).
  • The slave flip-flop is active when the clock is in the opposite phase (typically the falling edge or low level of the clock).

This arrangement ensures that any input to the flip-flop is first stored in the master flip-flop and then transferred to the slave flip-flop during the next clock phase. The output is taken from the slave flip-flop, ensuring the circuit is stable and free of glitches.

Key Components:

  • Master Flip-Flop: This flip-flop is triggered during the first phase of the clock and captures the input data.
  • Slave Flip-Flop: This flip-flop is triggered during the second phase of the clock, and it outputs the data captured by the master.

Operation of the Master-Slave Flip-Flop

  1. Clock High (Master Enabled, Slave Disabled):
    • During the high phase of the clock (positive edge or high level), the master flip-flop is enabled, and it captures the input state.
    • The output of the master flip-flop is passed to the slave flip-flop, but the slave remains disabled during this phase.
    • The slave flip-flop does not change its state during this clock phase.
  2. Clock Low (Master Disabled, Slave Enabled):
    • During the low phase of the clock (negative edge or low level), the master flip-flop is disabled, locking its state.
    • The slave flip-flop becomes enabled and takes the output from the master flip-flop as its input.
    • The slave flip-flop’s output is updated and becomes the final output of the entire master-slave flip-flop.
    • The output of the master-slave flip-flop changes only during this phase, ensuring that the flip-flop output remains stable throughout the clock cycle.

This setup ensures that the flip-flop changes its output only once per clock cycle, making it a synchronous circuit.

Types of Master-Slave Flip-Flops

  • Master-Slave SR Flip-Flop: Uses SR flip-flops in both the master and slave stages.
  • Master-Slave JK Flip-Flop: Uses JK flip-flops for the master and slave stages. It resolves the invalid state issue seen in the SR flip-flop and is commonly used due to its toggling capability.
  • Master-Slave D Flip-Flop: The D flip-flop form simplifies the design, ensuring that the output follows the input with one clock delay.

Master-Slave JK Flip-Flop Example

The Master-Slave JK Flip-Flop is a popular configuration due to its versatility. It operates as follows:

  1. When the clock is high:
    • The master flip-flop is active, and its output depends on the J and K inputs.
    • If J = 1 and K = 0, the master flip-flop sets the output to 1.
    • If J = 0 and K = 1, the master flip-flop resets the output to 0.
    • If J = K = 1, the master flip-flop toggles its state.
  2. When the clock goes low:
    • The master flip-flop is disabled, and the slave flip-flop becomes active.
    • The slave flip-flop takes the state from the master flip-flop as its input and outputs it.

This mechanism prevents any glitches from affecting the output, as inputs are only processed during specific phases of the clock.

Advantages of the Master-Slave Flip-Flop

  1. Race Condition Avoidance: In circuits without proper synchronization, changes in inputs can cause the output to oscillate or race between 0 and 1 states. The master-slave configuration ensures that input changes are registered in an orderly, controlled manner, reducing race conditions.
  2. Stable Output: The slave flip-flop holds the output stable during the clock phase when the master flip-flop is capturing the input. This ensures that the output only changes at a specific time during the clock cycle, preventing erratic behavior.
  3. Synchronous Operation: The master-slave flip-flop operates synchronously with the clock, ensuring that changes happen in alignment with the clock signal and thus preventing unwanted timing errors.
  4. Controlled Timing: The master-slave design ensures that changes in the flip-flop’s output occur only once per clock cycle, making it ideal for sequential circuits where precise timing is important.

Disadvantages of the Master-Slave Flip-Flop

  1. Complexity: The master-slave flip-flop involves two flip-flops for each state change, making it more complex than a simple edge-triggered flip-flop.
  2. Propagation Delay: Since the output changes only after the clock’s second phase (after the slave stage), there is a delay in the output response compared to single flip-flop designs.

Master-Slave Flip-Flop vs. Edge-Triggered Flip-Flop

Feature Master-Slave Flip-Flop Edge-Triggered Flip-Flop
Structure Two flip-flops (master and slave) Single flip-flop
Clock Dependency Changes output during opposite clock phase Changes output on clock edge
Delay Introduces an extra clock phase delay Faster, immediate response
Race Condition Avoids race conditions due to two-stage design May suffer race conditions without careful design

5.4 Flip-flop excitation table and design procedure.

Flip-flops are fundamental building blocks in digital electronics, and their design often involves determining how to transition from one state to another. This section will cover the excitation table for various types of flip-flops and the design procedure to implement them in circuits.

1. Flip-Flop Excitation Table

The excitation table defines the input conditions required to transition a flip-flop from its current state to its next state. Each type of flip-flop has its own excitation table based on its characteristics. Below are the excitation tables for the most common types of flip-flops: SR, JK, D, and T.

1.1 SR Flip-Flop Excitation Table

Present State (Q) Next State (Q<sub>next</sub>) S R
0 0 0 0
0 1 1 0
1 0 0 1
1 1 0 0
  • Notes:
    • S = Set input, R = Reset input.
    • The state (Q) can only change when the corresponding S or R inputs are active.

1.2 JK Flip-Flop Excitation Table

Present State (Q) Next State (Q<sub>next</sub>) J K
0 0 0 0
0 1 1 0
1 0 0 1
1 1 1 1
  • Notes:
    • J = Input to set the flip-flop.
    • K = Input to reset the flip-flop.
    • J = K = 1 results in toggling the state.

1.3 D Flip-Flop Excitation Table

Present State (Q) Next State (Q<sub>next</sub>) D
0 0 0
0 1 1
1 0 0
1 1 1
  • Notes:
    • D = Data input; the next state directly follows the D input.

1.4 T Flip-Flop Excitation Table

Present State (Q) Next State (Q<sub>next</sub>) T
0 0 0
0 1 1
1 0 1
1 1 0
  • Notes:
    • T = Toggle input; T = 1 causes the flip-flop to toggle its state.

2. Design Procedure for Flip-Flops

Designing a flip-flop circuit involves several steps, including defining the required state transitions, creating the excitation table, deriving the input equations, and implementing the circuit. Here’s a step-by-step guide:

2.1 Define the Requirements

  1. Determine the State Transitions: Identify the current state and the desired next state for each clock cycle.
  2. Create a State Diagram: Visualize the states and transitions to understand the behavior of the system.

2.2 Construct the Excitation Table

  1. Choose the Flip-Flop Type: Based on the requirements, select an appropriate flip-flop type (e.g., D, JK, or T).
  2. Create the Excitation Table: Fill in the excitation table based on the current and next states, as shown in the previous section.

2.3 Derive Input Equations

  1. Use Karnaugh Maps: Simplify the excitation conditions to derive the input equations for the selected flip-flop type using Karnaugh maps or Boolean algebra.
  2. Generate Logic Expressions: Create logic expressions for each input based on the excitation table and the derived equations.

2.4 Implement the Circuit

  1. Choose Logic Gates: Based on the logic expressions, select the appropriate logic gates (AND, OR, NOT) to construct the flip-flop.
  2. Draw the Circuit Diagram: Create a schematic diagram of the circuit using the chosen gates and flip-flops.

2.5 Simulation and Testing

  1. Simulate the Circuit: Use simulation software to verify the functionality of the circuit and check the state transitions against the expected behavior.
  2. Debugging: If the simulation does not match the expected results, debug the circuit, focusing on the input conditions and logic gate arrangements.

Example: Designing a JK Flip-Flop

Let’s say we want to design a JK flip-flop that transitions from states as follows:

Current State (Q) Next State (Q<sub>next</sub>)
0 1
1 0

Step 1: State Transition

  • From Q = 0 to Q<sub>next</sub> = 1 requires J = 1, K = 0.
  • From Q = 1 to Q<sub>next</sub> = 0 requires J = 0, K = 1.

Step 2: Excitation Table

Using the JK excitation table, we can determine the required inputs:

Present State (Q) Next State (Q<sub>next</sub>) J K
0 1 1 0
1 0 0 1

Step 3: Derive Input Equations

  • From the excitation table, we can derive:
    • J = Q’ (where Q’ is NOT Q)
    • K = Q

Step 4: Implement the Circuit

  • Using the derived logic:
    • Connect an inverter to the Q output to obtain Q’.
    • Use Q and Q’ as inputs to the JK flip-flop.

Step 5: Testing

  • Simulate the circuit to verify the state transitions and ensure the flip-flop operates as intended.

 

5.5 state diagram and simple sequential circuits

In digital design, state diagrams and sequential circuits are crucial for representing and implementing systems that depend on past states (memory). This section covers the concept of state diagrams and their application in designing simple sequential circuits.

1. State Diagram

A state diagram is a graphical representation of a finite state machine (FSM). It shows the various states of the system, the transitions between these states, and the conditions (inputs) that cause these transitions. State diagrams help visualize the behavior of sequential circuits.

Key Components of a State Diagram:

  • States: Represented as circles, each state indicates the status of the system at a given time.
  • Transitions: Arrows connecting states indicate how the system moves from one state to another. Each transition is triggered by specific input conditions.
  • Inputs/Outputs: Labels on the arrows can indicate the inputs that trigger the transitions or the outputs produced as a result of being in a state.

Example of a State Diagram:

Consider a simple state diagram for a binary counter that counts from 0 to 3 (00 to 11 in binary):

  1. States:
    • State 00 (S0)
    • State 01 (S1)
    • State 10 (S2)
    • State 11 (S3)
  2. Transitions: The counter increments on each clock pulse:
    • From S0 to S1 on input (clock).
    • From S1 to S2 on input (clock).
    • From S2 to S3 on input (clock).
    • From S3 to S0 on input (clock).
  3. State Diagram:
 +—-+ clock +—-+
| S0 | ——–> | S1 |
+—-+ +—-+
^ |
| |
| clock | clock
| |
+—-+ clock +—-+
| S3 | <——– | S2 |
+—-+ +—-+

2. Simple Sequential Circuits

A sequential circuit is a type of digital circuit whose output depends not only on the present input but also on the past sequence of inputs (i.e., the current state). Sequential circuits typically consist of flip-flops, logic gates, and sometimes combinational logic.

Basic Design Procedure for Sequential Circuits:

  1. Define Requirements:
    • Determine the desired behavior of the circuit, including inputs, outputs, and state transitions.
  2. Create a State Diagram:
    • Construct a state diagram to visualize the states and transitions based on the requirements.
  3. Construct the State Table:
    • Create a state table that lists the current state, next state, inputs, and outputs.
  4. Derive Excitation Conditions:
    • Using the excitation table for the chosen flip-flop type, derive the conditions needed to transition between states.
  5. Implement Logic Circuits:
    • Design the logic circuits required to create the flip-flops and combinational logic based on the derived equations.
  6. Simulate and Test:
    • Simulate the circuit to verify its operation and ensure it meets the specified requirements.

Example of a Simple Sequential Circuit:

Design a 2-bit Johnson Counter:

  1. Define Requirements:
    • A 2-bit Johnson counter will count in a specific sequence (00, 01, 11, 10) and then repeat.
  2. Create a State Diagram:
    • The states and transitions would be as follows:
      • S0 (00) to S1 (01)
      • S1 (01) to S3 (11)
      • S3 (11) to S2 (10)
      • S2 (10) to S0 (00)
  3. Construct the State Table:
Present State (Q1 Q0) Next State (Q1′ Q0′) Input Output
00 01 Clock 00
01 11 Clock 01
11 10 Clock 11
10 00 Clock 10
  1. Derive Excitation Conditions:
    • Using D flip-flops for the implementation:
      • Q1′ = D1 = Q0 (for Q1)
      • Q0′ = D0 = Q1′ (for Q0)
  2. Implement Logic Circuits:
    • Connect the D flip-flops based on the excitation conditions.
    • Create a circuit using AND, OR gates as necessary to generate the clock pulses.
  3. Simulate and Test:
    • Use simulation tools to verify the counter counts correctly through its states.

 

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